Our partner develops next gen AI accelerators at the intersection of semiconductors, photonics, and AI. The project focuses on verification of complex digital and mixed signal ASICs, including high speed interfaces and compute blocks, with an emphasis on building scalable SystemVerilog/UVM environments, constrained random and coverage driven methodologies, assertions, formal verification, and timing accurate simulations with SDF back annotation. The scope also covers PCIe, RISC V CPU subsystems, corner case analysis, block and system debug, plus FPGA prototyping and post silicon validation. The role requires strong expertise in digital design, processor architecture, and verification methodologies, along with solid debugging and system-level thinking skills.

Verification & Tools Environment

• SystemVerilog, UVM (scalable verification environment development).
• Full ASIC verification flow (block-level → full-chip).
• High-speed interface verification (PCIe) and CPU subsystems (RISC-V).  Simulation tools: Xcelium / VCS / Questa.
• Coverage-driven and formal verification (assertions, functional coverage).
• Netlist simulation with SDF back-annotation.
• FPGA prototyping and post-silicon validation.
• Debugging and system-level analysis of complex scenarios.